The exemplary embodiments of this invention relate generally to semiconductor devices and, more particularly, to a complementary metal oxide semiconductor device having a gate-all-around nanowire structure.
A complementary metal oxide semiconductor device (CMOS) uses symmetrically-oriented pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) arranged on silicon or silicon-on-insulator (SOI) substrates. Source and drain regions associated with each MOSFET are connected by a channel. A gate disposed adjacent the channel controls the flow of current between the source and drain regions. The channel may be defined by a thin “fin” or other structure that provides surface(s) through which the gate controls the flow of current.
In a device such as a gate-all-around (GAA) nanowire MOSFET, the channel between the source and drain regions is a nanowire, and the gate surrounds the nanowire. Formation of  such a gate so as to wrap around the nanowire is a challenge. For example, it is often difficult (if not impossible) to pattern the portion of the gate that is located underneath the nanowire. Hence, the bottom portion of the gate may become longer than the top portion and may overlap the source and drain regions of the device.
In fabricating a GAA nanowire MOSFET, a dummy gate is generally formed as a sacrificial structure to facilitate patterning to achieve a desired alignment and/or the implantation of ions for doping purposes. A replacement gate flow is then used to remove the dummy gate and install a permanent replacement gate. In the replacement gate flow, the dummy gate is patterned. The nanowire is then released from the dummy gate by the removal of the dummy gate. In removing the dummy gate, the material underneath the nanowire is undercut to cause the complete release of the wire from the material of the dummy gate and to form an opening that can be filled with a GAA structure. However, the undercutting also extends the opening in the directions toward the source and drain, thereby adding to the parasitic capacitance of the MOSFET.